1. Field of the Invention
Embodiments of the present invention generally relate to manufacturing semiconductor devices. More specifically, embodiments described herein relate to manufacture of floating gate NAND memory devices and other transistor gate dielectrics using an improved plasma applicator and process.
2. Description of the Related Art
Flash memory, such as NAND flash memory devices, is a commonly used type of non-volatile memory in widespread use for mass storage applications. The NAND flash memory devices typically have a stacked type gate structure in which a tunnel oxide (TO), a floating gate (FG), an inter-poly dielectric (IPD), and a control gate (CG) are sequentially stacked on a semiconductor substrate. The floating gate, the tunnel oxide, and the underlying portion of the substrate generally form a cell (or memory unit) of the NAND flash memory device. A shallow trench isolation (STI) region is disposed in the substrate between each cell adjacent to the tunnel oxide and the floating gate to separate the cell from adjacent cells. During writing of the NAND flash memory devices, a positive voltage is applied to the control gate which draws electrons from the substrate into the floating gate. For erasing data of the NAND flash memory devices, a positive voltage is applied to the substrate to discharge electrons from the floating gate and through the tunnel oxide. The flow of electrons is sensed by a sensing circuitry and results in the returns of “0” or “1” as current indicators. The amount of electrons in the floating gate and “0” or “1” characteristics form the basis for storing data in the NAND flash memory devices.
The floating gate is typically isolated from the semiconductor substrate by the tunnel oxide and from the control gate by the inter-poly dielectric, which prevents the leakage of electrons between, for example, the substrate and the floating gate or the floating gate and the control gate. To enable continued physical scaling of the NAND flash memory device, a nitridation process has been used by the industry to incorporate nitrogen into the surface of the floating gate to improve the reliability of the tunnel oxide or to suppress dopant diffusion out of the floating gate. The surface nitridation of the tunnel oxide is also desirable for minimizing the flat-band voltage (Vfb) shift and mobility degradation. Therefore, the percentage of the nitrogen at the floating gate and the tunnel oxide interface is critical to improve the NAND flash program window. For NAND Flash applications, it has been desirable to increase the interface N % concentration from nominally 3% to much higher levels of 6%-12%, which, however, requires high thermal budgets in excess of 1100° C. and 60 seconds. However, the manufacturers of NAND Flash memories typically prefer thermal budgets less than 1000° C. and 30 seconds to prevent the dopant in the floating gate from diffusing out. In addition, it has been observed that the nitridation process also undesirably incorporates nitrogen into shallow trench isolation regions. Nitrogen incorporated in the shallow trench isolation region between neighboring floating gate structures forms a charge leakage path which can negatively impact final device performance.
Therefore, there is a need for improved methods and an apparatus without having the above-mentioned issues.